The present invention relates to a multi-port memory, a semiconductor device that the multi-port memory has been loaded, and a memory macro-cell that is used as a library in an LSI (Large Scale Integrated circuit) design support system that designs the semiconductor device and in particular relates to the multi-port memory on which a test is favorably performed in a disturbed state and the semiconductor device and the memory macro-cell that are favorably utilized in the test that is performed on the multi-port memory concerned in the disturbed state.
In a test performed on a dual-port SRAM (Static Random Access Memory) (hereinafter, abbreviated as DP-SRAM), it is known that the so-called disturbed state where the same memory cell, that is, one memory cell is accessed from the both ports is one of the worst states that are reduced in operation timing margin. The disturbed state means a state where when a plurality of word lines that are coupled to the same memory cell have been activated, a read margin and/or a write margin from a port that has used one word line is/are more deteriorated than the margin(s) when the other word line is not activated. A port that is a test object will be called a test port and a port that activates the other word line will be called a disturb port.
In Japanese Unexamined Patent Application Publication No. 2010-80001 and Yuichiro Ishii, et al, “A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues”, IEEE J. Solid-State Circuits, U.S.A., Institute of Electrical and Electronics Engineers, November 2011, Vol. 46, No. 11, pp. 2535-2544, there are disclosed circuits of the type configured to adjust timings that the word lines on the disturb port side and the test port side are activated in order to appropriately give the disturbed state. When the word line on the disturb port side is activated and the disturbed state has reached its saturation level, the word line on the test port side is activated.
In Japanese Unexamined Patent Application Publication No. 2008-299991, there is disclosed a DP-SRAM that adjusts the timings that the word lines of two ports are activated on the basis of a delay control signal.
In Japanese Unexamined Patent Application Publication No. 2009-64532, a DP-SRAM to which a BIST (Built In Self Test) circuit has been coupled is disclosed. When a test mode signal that instructs simultaneous accessing from two ports is input, an address pattern generation circuit in the BIST circuit generates address signals AA[0:a] and AB[0:a] with which both of A and B ports select the same memory cell and supplies the address signals so generated to address input terminals of the A and B ports of the DP-SRAM.